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DAC8544IPFB bảng dữ liệu(PDF) 13 Page - Texas Instruments |
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DAC8544IPFB bảng dữ liệu(HTML) 13 Page - Texas Instruments |
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13 / 20 page ![]() www.ti.com THEORY OF OPERATION D/A SECTION _ + Resistor String VREF + VREF − DAC Register VOUT External Reference (–) External Reference (+) VFB R R V OUT + 2 V REF* ) (VREF) * VREF*) D 65536 (1) RESISTOR STRING VREF+ To Output Amplifier R R R R VREF– OUTPUT AMPLIFIER DAC8544 SLAS420 – MAY 2004 The architecture of the DAC8544 consists of four string DACs followed by an output buffer amplifier. Figure 30 shows a block diagram of the DAC architecture. Figure 30. DAC8544 Architecture The input coding to the DAC8544 is unsigned binary, which gives the ideal output voltage as: where • D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. The resistor string section is shown in Figure 31. It is simply a divide-by-two resistor, followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off, to be fed into the output amplifier, by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is assured monotonic. Figure 31. Resistor String The output buffer is capable of generating rail-to-rail voltages at its output, which gives an output range of 0 V to VREF+. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/ µs with a full-scale settling time of 10 µs with the output loaded. The feedback and gain setting resistors of the amplifier are in the order of 50 kΩ. Their absolute value can be off significantly, but they are matched to within 0.1%. The inverting input of the output amplifier is brought out to the VFB pin, through the feedback resistor. This allows for better accuracy in critical applications by tying the VFB point and the amplifier output together at the load. Other signal conditioning circuitry may also be connected between these points for specific applications including current sourcing. 13 |
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