These data possibilities are shown in

Figure 15 Note that

the justification of data depends on how the 10-bit data

word is located within the 16-bit data source (CPU) register

In either case there is a surplus of 6 bits and these are

All of these DACs load 10 bits on the 1st write cycle A

particular set of 2 bits is then overwritten on the 2nd write

cycle depending on the justification of the data For all left

justified data options the 1st write cycle must contain the

MS or Hi Byte data group

611 For Left Justified Data

For applications which require left justified data DAC1006 –

1008 can be used A simplified logic diagram which shows

the external connections to the data bus and the internal

functions of both of the data buffer registers (Input Latch

and DAC Register) is shown in

Figure 16

These

parts require the MS or Hi Byte data group to be transferred

on the 1st write cycle

62 Controlling Data Transfer for an 8-Bit Data Bus

Three operating modes are possible for controlling the

transfer of data from the Input Latch to the DAC Register

where it will update the analog output voltage The simplest

is the automatic transfer mode which causes the data

transfer to occur at the time of the 2nd write cycle This is

recommended when the exact timing of the changes of the

DAC analog output are not critical This typically happens

where each DAC is operating individually in a system and

the analog updating of one DAC is not required to be syn-

chronized to any other DAC For synchronized DAC updat-

ing two options are provided mP control via a common

XFER strobe or external update timing control via an exter-

nal strobe The details of these options are now shown

DAC100610071008 (20-Pin Parts for Left Justified Data)

TLH5688 – 16

FIGURE 15 Fitting a 10-Bit Data Word into 16 Available Bit Locations

TLH5688 – 17

FIGURE 16 Input Connections and Controls for DAC100610071008 Left Justified Data

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