USBN9604SLB datasheet(46/60 Pages) NSC

46 / 60 page

7.0 Register Set (Continued)

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7.2.20

Endpoint Control X Register (EPC1 to EPC6)

Each unidirectional endpoint has an EPCx register with the bits defined below.

Endpoint. This field holds the 4-bit endpoint address.

EP_EN

Endpoint Enable. When this bit is set, the EP3-0 field is used in address comparison, together with the AD6-0 field in the

FAR register. See Section 6.2 for a description. When cleared, the endpoint does not respond to any token on the USB bus.

Note: AD_EN in the FAR register is the global address compare enable for the device. If it is cleared, the device does not

respond to any address, regardless of the EP_EN state.

ISO

Isochronous. When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not

ready but enabled; i.e. if an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is re-

ceived and the FIFO is full since there is no USB handshake for isochronous transfers.

STALL

Setting this bit causes the chip to generate STALL handshakes under the following conditions:

1. The transmit FIFO is enabled and an IN token is received.

2. The receive FIFO is enabled and an OUT token is received.

Setting this bit does not generate a STALL handshake in response to a SETUP token.

7.2.21

Transmit Status X Register (TXS1, TXS2, TXS3)

Each of the three transmit endpoint FIFOs has a Transmit Status register with the bits defined below.

TCOUNT

Transmission Count. This bit indicates the count of empty bytes available in the FIFO. If this count is greater than 31, a value

of 31 is reported.

TX_DONE

Transmission Done. When set, this bit indicates that the endpoint responded to a USB packet. Three conditions can cause

this bit to be set:

A data packet completed transmission in response to an IN token with non-ISO operation.

2. The endpoint sent a STALL handshake in response to an IN token

3. A scheduled ISO frame was transmitted or discarded.

This bit is cleared when this register is read.

ACK_STAT

Acknowledge Status. This bit is interpreted when TX_DONE is set. Its function differs depending on whether ISO (ISO in the

EPCx register is set) or non-ISO operation (ISO is reset) is used.

For non-ISO operation, this bit indicates the acknowledge status (from the host) about the ACK for the previously sent pack-

et. This bit itself is set when an ACK is received; otherwise, it is cleared.

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

STALL

Reserved

ISO

EP_EN

EP3-0

000000

r/w

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TX_URUN

ACK_STAT

TX_DONE

TCOUNT4-0

0000

CoR

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