CPC7691BA datasheet(10/16 Pages) IXYS

10 / 16 page

INTEGRATED CIRCUITS DIVISION

www.ixysic.com

R01

CPC7691

As can be seen in "Figure 1. CPC7691 Block Diagram” on

page 1 the TSD control bypasses the latch, therefore

the TSD control functions are independent of the latch.

On designs that do not wish to individually control the

LATCH pins of multiple-port cards it is possible to bus

many (or all) of the LATCH pins together to create a

single, board-level enable control. The weak internal

pull-up allows a fan out of up to 32 when the system’s

LATCH control driver has a logic low minimum sink

capability of 4mA.

2.4 TSD Pin Description

The TSD pin is a bidirectional I/O structure with an

internal pull-up current source biased from VDD having

a nominal value of 16

A.

As an output, this pin indicates the status of the

thermal shutdown circuitry. During normal operation

this pin will be pulled up to VDD, but under fault

conditions that create excess thermal loading, the

CPC7691 will enter thermal shutdown, and a logic low

will be output at the TSD pin.

As an input, TSD is utilized to place the CPC7691 into

the “All-Off” state. This is accomplished by simply

pulling TSD to a TTL input logic low level. When used

as an input, forcing a logic high condition at TSD will

not override the thermal shutdown capability.

As discussed earlier the TSD control bypasses the

latch so that neither the input nor the output control

functions are affected by the latch. Consequently,

because TSD is independent of the latch, the internal

thermal shutdown function and the external “All-Off”

control features are not affected by the state of the

LATCH input.

For applications using low-voltage logic devices (lower

than VDD), IXYS Integrated Circuits Division

recommends the use of an open-collector or an

open-drain type output to control TSD. This avoids

sinking the TSD pull-up bias current to ground during

normal operation when the All-Off state is not

required. In general, IXYS Integrated Circuits Division

recommends all applications use an open-collector or

open-drain type device to drive this pin.

2.5 Under Voltage Switch Lock Out Circuitry

2.5.1 Overview

Smart logic in the CPC7691 now provides for switch

state control during both power-up and power loss

transitions. An internal detector is used to evaluate the

VDD supply to determine when to de-assert the under

voltage switch lock out circuitry with a rising VDD and

when to assert the under voltage switch lock out

circuitry with a falling VDD. Any time an unsatisfactory

low VDD condition exists, the under voltage lock out

circuit overrides user switch control by blocking the

information at the external input pins, and conditioning

internal switch commands to the All-Off state. Upon

restoration of VDD, the switches will remain in the

All-Off state until the LATCH input is pulled low.

The rising VDD switch lock-out release threshold is

internally set to ensure all internal logic is properly

biased and functional before accepting external switch

commands at the inputs to control the switch states.

For a falling VDD event, the lock-out threshold is set to

assure proper logic and switch behavior up to the

moment the switches are forced off and external

inputs are suppressed.

To facilitate hot plug insertion and system power-up

state control, the LATCH pin has an integrated weak

pull-up sourced from the VDD power rail that will hold a

non-driven LATCH pin at a logic high state. This

enables board designers to use the CPC7691 with

FPGAs or other devices that provide high impedance

outputs during power-up and logic configuration.

2.5.2 Hot Plug and power-up Design Considerations

There are six possible start-up scenarios that can

occur during power-up with TSD  0. They are:

INRINGING defined at power-up & LATCH = 0

INRINGING defined at power-up & LATCH = 1

INRINGING defined at power-up & LATCH = Z

INRINGING not defined at power-up & LATCH = 0

INRINGING not defined at power-up & LATCH = 1

INRINGING not defined at power-up & LATCH = Z

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