PCI9060 datasheet(7/192 Pages) ETC

7 / 192 page

PCI 9080

TABLE OF CONTENTS

©PLX Technology, Inc., 1997

Page viii

Version 1.01

4.6.7

(DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register..................................................................... 81

4.6.8

(DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register ................................................................. 81

4.6.9

(DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register ........................................................... 81

4.6.10

(DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register .............................................................. 81

4.6.11

(DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register ............................................................... 82

4.6.12

(DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register ............................................................... 82

4.6.13

(DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Register............................................................................................. 82

4.6.14

(DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register .............................................................................................. 83

4.7

MESSAGING QUEUE REGISTERS.......................................................................................................................84

4.7.1

(OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register............................................................. 84

4.7.2

(OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register.............................................................. 84

4.7.3

(IQP; PCI:40h) Inbound Queue Port Register................................................................................................................... 84

4.7.4

(OQP; PCI:44h) Outbound Queue Port Register .............................................................................................................. 85

4.7.5

(MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register ........................................................................ 85

4.7.6

(QBAR; PCI:C4h, LOC:144h) Queue Base Address Register .......................................................................................... 85

4.7.7

(IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register ................................................................................ 86

4.7.8

(IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register .................................................................................. 86

4.7.9

(IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register ................................................................................ 86

4.7.10

(IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register.................................................................................... 86

4.7.11

(OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register ............................................................................ 87

4.7.12

(OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register .............................................................................. 87

4.7.13

(OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register ............................................................................ 87

4.7.14

(OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register ............................................................................... 87

4.7.15

(QSR; PCI:E8h, LOC:168h) Queue Status/Control Register ............................................................................................ 88

PIN DESCRIPTION ........................................................................................................................................................89

5.1

PIN SUMMARY .......................................................................................................................................................89

5.2

PIN OUT COMMON TO ALL BUS MODES............................................................................................................90

5.3

C BUS MODE PIN OUT ..........................................................................................................................................94

5.4

J BUS MODE PIN OUT...........................................................................................................................................96

5.5

S BUS MODE PIN OUT ..........................................................................................................................................98

ELECTRICAL SPECIFICATIONS................................................................................................................................100

PACKAGE, SIGNAL, AND PIN OUT SPECS............................................................................................................103

7.1

PACKAGE MECHANICAL DIMENSIONS ............................................................................................................103

7.2

TYPICAL PCI BUS MASTER ADAPTER..............................................................................................................104

7.3

9080 PIN OUT (S, J, AND C MODES)..................................................................................................................105

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