COP8SA datasheet(14/60 Pages) NSC

14 / 60 page

5.0 Pin Descriptions

COP8SAx I/O structure minimizes external component re-

quirements. Software-switchable I/O enables designers to

reconfigure the microcontroller’s I/O functions with a

single instruction. Each individual I/O pin can be indepen-

dently configured as an output pin low, an output high, an

input with high impedance or an input with a weak pull-up

device. A typical example is the use of I/O pins as the key-

board matrix input lines. The input lines can be pro-

grammed with internal weak pull-ups so that the input

lines read logic high when the keys are all up. With a key

closure, the corresponding input line will read a logic zero

since the weak pull-up can easily be overdriven. When the

key is released, the internal weak pullup will pull the input

line back to logic high. This flexibility eliminates the need

for external pull-up resistors. The High current options are

available for driving LEDs, motors and speakers. This

flexibility helps to ensure a cleaner design, with less exter-

nal components and lower costs. Below is the general de-

scription of all available pins.

CC and GND are the power supply pins. All VCC and

GND pins must be connected.

CKI is the clock input. This can come from the Internal

R/C oscillator, external, or a crystal oscillator (in conjunc-

tion with CKO). See Oscillator Description section.

RESET is the master reset input. See Reset description

section.

The device contains four bidirectional 8-bit I/O ports (C, G,

L and F), where each individual bit may be independently

configured as an input (Schmitt trigger inputs on ports L

and G), output or TRI-STATE under program control.

Three data memory address locations are allocated for

each of these I/O ports. Each I/O port has two associated

8-bit memory mapped registers, the CONFIGURATION

address is also reserved for the input pins of each I/O

port. (See the memory map for the various addresses as-

sociated with the I/O ports.)

Figure 5 shows the I/O port

configurations. The DATA and CONFIGURATION regis-

ters allow for each port bit to be individually configured un-

der software control as shown below:

CONFIGURATION

DATA

Port Set-Up

Hi-Z Input

(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on

the inputs.

Port L supports the Multi-Input Wake Up feature on all eight

pins. The 16-pin device does not have a full complement of

Port L pins. The unavailable pins are not terminated. A read

operation these unterminated pins are not terminated. A read

operation these unterminated pins will return unpredictable

values. To minimize current drain, the unavailable pins must

be programmed as outputs.

Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O

ports. Pin G6 is always a general purpose Hi-Z input. All pins

have Schmitt Triggers on their inputs. Pin G1 serves as the

dedicated WDOUT WATCHDOG output with weak pullup

if WATCHDOG feature is selected by the ECON register.

The pin is a general purpose I/O if WATCHDOG feature is

not selected. If WATCHDOG feature is selected, bit 1 of the

Port G configuration and data register does not have any ef-

fect on Pin G1 setup. Pin G7 is either input or output depend-

ing on the oscillator option selected. With the crystal oscilla-

tor option selected, G7 serves as the dedicated output pin for

the CKO clock output. With the internal R/C or the external

oscillator option selected, G7 serves as a general purpose

Hi-Z input pin and is also used to bring the device out of

HALT mode with a low to high transition on G7. There are

two registers associated with Port G, a data register and a

configuration register. Using these registers, each of the 5

I/O pins (G0, G2–G5) can be individually configured under

software control.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin (crystal clock option) or general purpose in-

put (R/C or external clock option), the associated bits in the

data and configuration registers for G6 and G7 are used for

special purpose functions as outlined below. Reading the G6

and G7 data bits will return zeroes.

The device will be placed in the HALT mode by writing a “1”

to bit 7 of the Port G Data Register. Similarly the device will

be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register en-

ables the MICROWIRE/PLUS to operate with the alternate

phase of the SK clock. The G7 configuration bit, if set high,

enables the clock start up delay after HALT when the R/C

clock configuration is used.

Config. Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G0 INTR (External Interrupt Input)

Port G has the following dedicated functions:

G7 CKO Oscillator dedicated output or general purpose in-

put

G1 WDOUT WATCHDOG and/or CLock Monitor if WATCH-

DOG enabled, otherwise it is a general purpose I/O

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated. A read operation on these unterminated pins

will return unpredictable values. Only the COP8SAC7 device

contains Port C. The 20/28 pin devices do not offer Port C.

On these devices, the associated Port C Data and Configu-

ration registers should not be used.

Port F is an 8-bit I/O port. The 28-pin device does not have

a full complement of Port F pins. The unavailable pins are

not terminated. A read operation on these unterminated pins

will return unpredictable values.

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