MPC875 datasheet(51/84 Pages) FREESCALE

51 / 84 page

MPC875/MPC870 Hardware Specifications, Rev. 3.0

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

CPM Electrical Characteristics

L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time)

35.00

—

L1RSYNCB, L1TSYNCB rise/fall time

—

15.00

L1RXDB valid to L1CLKB edge (L1RXDB setup time)

17.00

—

L1CLKB edge to L1RXDB invalid (L1RXDB hold time)

13.00

—

L1CLKB edge to L1ST1 and L1ST2 valid 4

10.00

45.00

78A

L1SYNCB valid to L1ST1 and L1ST2 valid

10.00

45.00

L1CLKB edge to L1ST1 and L1ST2 invalid

10.00

45.00

L1CLKB edge to L1TXDB valid

10.00

55.00

80A

L1TSYNCB valid to L1TXDB valid 4

10.00

55.00

L1CLKB edge to L1TXDB high impedance

0.00

42.00

L1RCLKB, L1TCLKB frequency (DSC =1)

—

16.00 or

SYNCCLK

MHz

L1RCLKB, L1TCLKB width low (DSC =1)

P + 10

—

83a

L1RCLKB, L1TCLKB width high (DSC = 1)3

P + 10

—

L1CLKB edge to L1CLKOB valid (DSC = 1)

—

30.00

L1RQB valid before falling edge of L1TSYNCB4

1.00

—

L1TCLK

L1GRB setup time2

42.00

—

L1GRB hold time

42.00

—

L1CLKB edge to L1SYNCB valid (FSD = 00) CNT = 0000, BYT = 0,

DSC = 0)

—0.00

1 The ratio SyncCLK/L1RCLKB must be greater than 2.5/1.

2 These specs are valid for IDL mode only.

3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.

4 These strobes and TxD on the first bit of the frame become valid after the L1CLKB edge or L1SYNCB, whichever

comes later.

Table 21. SI Timing (continued)

Num

Characteristic

All Frequencies

Unit

Min

Max

MPC875 bảng dữ liệu(PDF) 51 Page - Freescale Semiconductor, Inc

MPC875 bảng dữ liệu(HTML) 51 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

bảng dữ liệu tải về

Link URL