MAC7100EC datasheet(23/48 Pages) MOTOROLA

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MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Electrical Characteristics

3.10 Analog-to-Digital Converter Characteristics

Table 24 and Table 25 show conditions under which the ATD operates. The following constraints exist to

obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists because the

sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside

of this range it will effectively be clipped.

3.10.1 Factors Influencing Accuracy

Three factors — source resistance, source capacitance and current injection — have an influence on the

accuracy of the ATD.

Table 24. ATD Operating Characteristics in 5 V Range

Conditions shown in Table 6 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

D Reference Potential

Low

High

VRL

VRH

VSSA

VDDA ÷ 2

—

VDDA ÷ 2

VDDA

C Differential Reference Voltage 1

1 Full accuracy is not guaranteed when differential voltage is less than 4.50 V

VRH – VRL

4.50

5.00

5.25

D ATD Clock Frequency

fATDCLK

0.5

—

2.0

MHz

D ATD 10-bit Conversion PeriodClock Cycles 2

@ 2.0MHz fATDCLK

2 Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.

NCONV10

TCONV10

—

Cycles

µs

D ATD 8-bit Conversion PeriodClock Cycles 2

@ 2.0MHz fATDCLK

NCONV8

TCONV8

—

Cycles

µs

D Recovery Time (VDDA = 5.0 V)

tREC

——

µs

P Reference Supply current 1 ATD module enabled

IREF

——

0.375

P Reference Supply current 2 ATD modules enabled

IREF

——

0.750

Table 25. ATD Operating Characteristics in 3.3 V Range

Conditions shown in Table 6, with VDDX = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted.

Num C

Rating

Symbol

Min

Typ

Max

Unit

D Reference Potential

Low

High

VRL

VRH

VSSA

VDDA ÷ 2

—

VDDA ÷ 2

VDDA

C Differential Reference Voltage 1

1 Full accuracy is not guaranteed when differential voltage is less than 3.0 V

VRH–VRL

3.0

3.3

3.6

D ATD Clock Frequency

fATDCLK

0.5

—

2.0

MHz

D ATD 10-bit Conversion PeriodClock Cycles 2

Conv, Time at 2.0MHz ATD Clock fATDCLK

2 Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.

NCONV10

TCONV10

—

Cycles

µs

D ATD 8-bit Conversion PeriodClock Cycles 2

Conv, Time at 2.0MHz ATD Clock fATDCLK

NCONV8

TCONV8

—

Cycles

µs

D Recovery Time (VDDA=5.0 V)

tREC

——

µs

P Reference Supply current 1 ATD module enabled

IREF

——

0.375

P Reference Supply current 2 ATD modules enabled

IREF

——

0.250

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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