LTC3206EUF datasheet(8/16 Pages) LINER

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LTC3206

3206f

Byte Format

Each byte sent to the LTC3206 must be 8 bits long followed

by an extra clock cycle for the Acknowledge bit to be

returned by the LTC3206. The data should be sent to the

LTC3206 most significant bit (MSB) first.

Acknowledge

The Acknowledge bit is used for handshaking between the

master and the slave. An Acknowledge (active LOW)

generated by the slave (LTC3206) lets the master know

that the latest byte of information was received. The

Acknowledge related clock pulse is generated by the

master. The master releases the SDA line (HIGH) during

the Acknowledge clock cycle. The slave-receiver must pull

down the SDA line during the Acknowledge clock pulse so

that it remains a stable LOW during the HIGH period of this

clock pulse.

Slave Address

The LTC3206 responds to only one 7-bit address which

has been factory programmed to 0011011. The eighth bit

of the address byte (R/W) must be 0 for the LTC3206 to

recognize the address since it is a write only device. This

is equivalent to an 8-bit address where the least significant

bit of the address is always 0. If the correct seven bit

address is given but the R/W bit is 1, the LTC3206 will not

respond.

Bus Write Operation

The master initiates communication with the LTC3206

with a START condition and a 7-bit address followed by the

Write Bit R/W = 0. If the address matches that of the

LTC3206, the LTC3206 returns an Acknowledge. The

master should then deliver the most significant data byte.

Again the LTC3206 acknowledges and the cycle is re-

peated two more times for a total of one address byte and

three data bytes. Each data byte is transferred to an

internal holding latch upon the return of an Acknowledge.

After all three data bytes have been transferred to the

LTC3206, the master may terminate the communication

with a STOP condition. Alternatively, a REPEAT-START

condition can be initiated by the master and another chip

on the I2C bus can be addressed. This cycle can continue

indefinitely and the LTC3206 will remember the last input

of valid data that it received. Once all chips on the bus have

been addressed and sent valid data, a STOP condition can

be sent and the LTC3206 will update its command latch

with the data that it had received.

In certain circumstances, the data on the I2C bus may

become corrupted. In these cases the LTC3206 responds

appropriately by preserving only the last set of complete

data that it has received. For example, assume the LTC3206

has been successfully addressed and is receiving data

when a STOP condition mistakenly occurs. The LTC3206

will ignore this stop condition and will not respond until a

new START condition, correct address, new set of data

and STOP condition are transmitted.

Likewise, if the LTC3206 was previously addressed and

sent valid data but not updated with a STOP, it will respond

to any STOP that appears on the bus independent of the

number of REPEAT-STARTs that have occurred. An ex-

ception occurs if a REPEAT-START is given and the

LTC3206 successfully acknowledges its addressed. In

this case, it will not respond to a STOP after the first data

byte is acknowledged. It will, however, respond after the

third data byte is acknowledged.

OPERATIO

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