COP888GD datasheet(6/42 Pages) NSC

6 / 42 page

AC Electrical Characteristics (Continued)

Note 12: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC

and outputs driven low but not connected to a load.

Note 13: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of IDD HALT is done with device

neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load;

all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up

CKI during HALT in crystal clock mode.

Note 14: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into

programming mode.

Note 15: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages VCC and the pins will have sink current to VCC when

biased at voltages VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins

will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD

transients.

Note 16: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 17: Parameter characterized but not tested.

COP888GD bảng dữ liệu(PDF) 6 Page - National Semiconductor (TI)

COP888GD bảng dữ liệu(HTML) 6 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

bảng dữ liệu tải về

Link URL