ICS93732 datasheet(4/8 Pages) ICST

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Giải thích chi tiết về linh kiện	Low Cost DDR Phase Lock Loop Zero Delay Buffer

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ICS93732

0578H—02/19/04

Notes:

Refers to transition on noninverting output.

While the pulse skew is almost constant over frequency, the duty cycle error

increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where

the cycle (tc) decreases as the frequency goes up.

Timing Requirements

TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Clock Frequency

freqop

Input Voltage level: 0-2.50V

340

MHz

Input Clock Duty Cycle

dtin

Clock Stabilization

tSTAB

from VDD = 2.5V to 1% target frequency

100

µs

1. Guaranteed by design, not 100% tested in production.

Switching Characteristics

TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

66 MHz

100

120

100 / 125/ 133/167MHz

200/267MHz

Phase Error

tpe

-150

150

Output to output Skew

Tskew

100

66 MHz to 100MHz

49.5

50.5

101MHz to 267 MHz

49.4

Rise Time, Fall Time

tR , tf

Load=120

Ω/14pF

579

950

tc-c

Duty Cycle (Sign Ended)

1,3

Cycle to cycle Jitter

1,2

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