Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
70
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
only be input from GPIO input pins (Global Input Bus).
There is no way to enable the SS_internally. In SPI
modes 2 & 3, where SS is not required between each
byte, the external pin may be grounded.
Important
: The AUX Out Enable bit (bit 5) of the Output
Register (DCA04OU-DCA07OU) must be set to 0 to dis-
able it.
9.5.9.4
Outputs
The function output is the MISO (master-in, slave-out)
signal, which may be driven on the Global Output bus
and is selected by Output Register (DCA04OU-
DCA07OU).
9.5.9.5
Interrupts
When enabled, the function generates an interrupt on
RX Reg Full status (Data Register 2 full). If Mode[1] of
the Function Register is set, the interrupt will be gener-
ated on SPI Complete status.
9.5.9.6
Usage Notes
1.
Reading the Status
Reading Control Register 0, which contains the sta-
tus bits, automatically resets the status bits to 0 with
the exception of TX Reg Empty, which is cleared
when a byte is written to the TX Data Register (Data
Register 1), and the RX Reg Full, which is cleared
when a byte is read from the RX Data Register
(Data Register 2).
2.
Multi-Slave Environment
The SS_ signal does not have any affect on the out-
put from the slave. The output of the slave at the
end of a reception/transmission is always the first bit
sent (the MSB, unless LSBF option is selected, then
it’s the LSB). To implement a multi-slave environ-
ment, a GPIO interrupt may be configured on the
SS_ input, and the Slave output strength may be
toggled between driving and High Z in firmware.
3.
Using Interrupts
RX Reg Full status or SPI Complete status gener-
ates an interrupt. Executing the interrupt routine
does not automatically clear status. If SPI Complete
is selected as the interrupt source, Control Register
0 (status) must be read in the interrupt routine to
clear the status. If RX Reg Full status is selected, a
byte must be read from the RX Data Register (Data
Register 2) to clear the status. If the interrupting sta-
tus is not cleared further interrupts will be sup-
pressed.
4.
Synchronization of CPU Interaction
Because the SPI Slave is clocked asynchronously
by the master SCLK, transfer of data between the
TX Register to shifter and shifter to RX Register
occurs asynchronously.
Either polling or interrupts can be used to detect that
a byte has been received and is ready to read. How-
ever, on the TX side, the user is responsible for
implementing a protocol that ensures there is
enough set-up time from the TX Data Register write
to the first clock (mode 2, 3) or SS_ (mode 0, 1) from
the master.
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