CLC949ACQ datasheet(6/12 Pages) NSC

6 / 12 page

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Figure 3: Transformer Coupled Input

Since the transformer response does not extend to DC it

is not an effective solution for applications which require

DC coupled inputs.

To drive the input of the CLC949, and retain DC

information, an amplifier configuration is required.

Comlinear suggests the use of the circuit shown in Figure 4.

This circuit is used on the E949PCASM.

Figure 4: Amplifier Coupled Input

In this circuit U7 buffers the analog input with a gain of

+1, and U6 buffers the input with a gain of -1.

The

circuit has been designed so that U6 and U7 have the

same loop gain, thereby offering the best possible match

of their AC characteristics. U5 is used to generate the

required offset voltages which are summed into the input

signal via U6 and U7. The CLC409 was selected for U6

and U7 due to its current feedback topology which allows

for very low distortion even at high frequencies, and its

excellent phase linearity. Phase match between U6 and

U7 is critical for good pulse response. To generate the

D.C. offsets, the CLC428 dual Op-amp was selected.

The CLC428 is a voltage-feedback op amp with very

good DC characteristics, and the large bandwidth makes

the output impedance low over a wide range of frequen-

cies, allowing good AC performance.

Regardless of how the input is driven, a small capacitor

(15pF) should be added from the VINP and VINN

terminals to GND. This will help to reduce the current

transients that are generated by the CLC949 inputs

during sampling.

Reference Generation

The CLC949 has internally generated reference

voltages. To use these references, you must externally

connect

the reference inputs by shorting VREFPO to

VREFP and VREFNO to VREFN. During the conversion

cycle, the impedance on these four pins varies

dynamically. To maintain stable biases on these pins you

must bypass them with 0.1

µF to GND. If you want to pro-

vide an external reference, then you have to be careful

to provide low output impedance drivers to the VREFP and

VREFN pins. Bypass capacitors on all reference pins are

recommended for best performance.

Bias Control

One of the unique features of the CLC949 is that it allows

you to set the internal bias current of the device. When

designing an A/D converter a tradeoff is made between

the

amount

power

dissipated

and

the

performance.

The CLC949 allows you to make this

tradeoff yourself. The bias current is controlled by the

pins BC0 and BC1. These two pins are digital input pins

from which one of three discrete bias points may be

selected (see truth table on page 4 of this datasheet) or

an external bias may be provided through the analog bias

control pin BIASC. If BC0 and BC1 are left open, they

will drift low and provide the default bias condition which

results in 220mW of dissipation at 20MHz sampling rate.

The actual power dissipated by the device is a function

of both the bias condition and the sample rate.

The

relationship between power and speed is shown for the

three discrete bias points in Figure 5.

Figure 5: Power Dissipation vs. Sample Rate

As the bias is turned up, the ability of the CLC949 to

handle high frequency inputs and the power dissipation

of the CLC949 increases. To use the BIASC pin, attach

a resistor from the pin to VDDA. The current drawn by this

resistor is mirrored in the device to set the internal bias

currents. A smaller value resistor will result in higher bias

currents and higher performance.Beyond a certain

point, additional improvement is not seen, although

power continues to increase.

For this reason, it is

recommended that bias setting resistors of less than

10K not be used. To generate the graph in Figure 6 a

CLC949 was set to sample a signal 1dB below full scale

U5A

CLC428

1.25k

U5B

CLC428

CLC409

500

Ω

500

Ω

400

Ω

500

Ω

400

Ω

R30

Ω

R27

Ω

CLC409

R29

400

Ω

R26

Ω

VREFMO

VINP

VINN

CLC949

R10

Ω

VIN

15pF

+5V

400

Ω

+5V

400

Ω

VINP

Ω

VREFMO

VINN

TM01-1T

VIN

CLC949

15pF

Power Dissipation vs. Sample Rate

Sample Rate (Hz)

400

300

100k

10M

100

200

High Bias

40M

Medium Bias

Low Bias

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