GMS30C7201 datasheet(77/352 Pages) HYNIX

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SDRAM Controller

8-5

GMS30C7201 Data Sheet

8.4

SDRAM Control Registers

The SDRAM controller has three registers: the configuration, refresh timer and the Write Buffer

Flush timer. The configuration register’s main function is to specify the number of SDRAMs

connected, and whether they are 2- or 4-bank devices. The refresh timer gives the number of

BCLK ticks that need to be counted in-between each refresh period. The Write Buffer Flush

timer is used to set the number of BCLK ticks since the last write operation, before the write

buffer’s contents are transferred to SDRAM.

In addition to the SDRAM control registers, the ARM may access the SDRAM mode registers

by writing to a 64MByte address space referenced from the SDRAM mode register base

address. Writing to the SDRAM mode registers is discussed further in 8.5 Power-up

Initialization of the SDRAMs on page 8-10.

8.4.1 Configuration Register

Address:

SDRAM register base address

The SDRAM controller configuration register is a 32-bit wide split read/write register, such that

bits [23:0] should be configured by the ARM, and bits [31:24] provide status information that

are read-only.

All locations containing “-” are for future expansion, and should always be programmed with

the binary value 0. Writes to bits [31:24] are always ignored.

E[3:0]

Device Enable - indicates that there is a physical SDRAM present in each of

the four slots in the address map. This bit is used to determine whether an

auto-refresh command should be issued to a particular memory device.

slot 0 - address range 0–16Mbyte

slot 1 - address range 16–32MByte

slot 2 - address range 32–48MByte

slot 3 - address range 48–64MByte

Value = 1 if a device is present

Value = 0 if a device is not present

B[3:0]

Indicates whether the SDRAM in the slot is a 2- or 4-bank device

Value = 1 if a four-bank device

Address

Name

Description

SDRAMCBase + 0x00

ConfigReg

#32-bit R/W

SDRAMCBase + 0x04

RefreshTmr

#16-bit R/W

SDRAMCBase + 0x08

Write buffer flush timer

#3-bit R/W

Table 8-4: SDRAM controller registers

S1 S0 ---

C1 C0 DC W PE3 B3 --

E2 B2 --

E1 B1 --

E0 B0 --

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