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PIC16F876ATI/ML bảng dữ liệu(PDF) 153 Page - Microchip Technology |
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PIC16F876ATI/ML bảng dữ liệu(HTML) 153 Page - Microchip Technology |
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153 / 234 page  2003 Microchip Technology Inc. DS39582B-page 151 PIC16F87XA FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK) TRISD 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISE 73A 74A 76A 77A 0000 -111 0000 -111 uuuu -uuu PIE1 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu PIE2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u PCON 73A 74A 76A 77A ---- --qq ---- --uu ---- --uu SSPCON2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu PR2 73A 74A 76A 77A 1111 1111 1111 1111 1111 1111 SSPADD 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu SSPSTAT 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu TXSTA 73A 74A 76A 77A 0000 -010 0000 -010 uuuu -uuu SPBRG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu CMCON 73A 974 76A 77A 0000 0111 0000 0111 uuuu uuuu CVRCON 73A 74A 76A 77A 000- 0000 000- 0000 uuu- uuuu ADRESL 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 73A 74A 76A 77A 00-- 0000 00-- 0000 uu-- uuuu EEDATA 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EEADR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EEDATH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EEADRH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EECON1 73A 74A 76A 77A x--- x000 u--- u000 u--- uuuu EECON2 73A 74A 76A 77A ---- ---- ---- ---- ---- ---- TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition, r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-5 for Reset value for specific condition. TPWRT TOST VDD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset |
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