TAS3002 datasheet(43/74 Pages) TI

43 / 74 page

7–3

Bass and treble cannot download in this mode. Mixer1 and Mixer2 registers can download in this mode or normal

mode (FL bit = 0).

Once the download is complete, the fast load bit must be cleared by writing a 0 into bit 7 of main control register 1

(MCR1). This puts the TAS3002 device into normal mode.

7.2.5

Codec Reset

During initialization, the output of the codec is disabled. Throughout reset and initialization, the output of the DAC is

muted to prevent extraneous noise being sent to the system output.

Data from the ADC and other internal processing is purged so that when reset/initialization is complete, only valid

inputs are sent to the system output.

7.3

Power-Down Mode

The TAS3002 device has an asynchronous power-down mode. In the power-down mode, the internal control

registers and equalization programming of the device are stored in the device.

To enter power-down mode:

Assert the power-down control signal (1)

Set the serial audio input clocks to 0

The TAS3002 device goes into power-down mode.

To exit the power-down mode:

Assert RESET (logic 0)

Restart the serial audio clocks

Wait for a delay of 1.0 ms (to allow the PLL to lock)

Negate the power-down control signal (logic 0)

Negate RESET (logic 1)

The device then returns to the state it was in before power down (resumes normal operation).

TAS3002 bảng dữ liệu(PDF) 43 Page - Texas Instruments