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CLC018 bảng dữ liệu(PDF) 7 Page - National Semiconductor (TI) |
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CLC018 bảng dữ liệu(HTML) 7 Page - National Semiconductor (TI) |
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7 / 18 page ![]() Timing Diagrams (Continued) Operation INPUT INTERFACING The inputs to the CLC018 are high impedance differential in- puts (see the equivalent input circuit in Figure 4). The CLC018 can be operated with either ECL or PECL (+5V ref- erenced ECL), depending upon the power supply connec- tions. The inputs are differential and must both be within the range of V CC– 2VtoVCC + 0.4V in order to function properly. SINGLE ENDED INPUTS Differential inputs are the preferred method of providing data to the CLC018, however, there are times when the only sig- nal available is single ended. To use the CLC018 with a single ended input, the unused input pin needs to be biased at a point higher than the low logic level, and lower than the high logic level. For best noise performance, the middle of DS100088-12 FIGURE 3. Timing Diagram — Switch Configuration DS100088-13 FIGURE 4. Equivalent Input Circuit www.national.com 7 |
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