CLC016ACQ datasheet(16/20 Pages) NSC

16 / 20 page

Product Description (Continued)

PCB LAYOUT RECOMMENDATIONS

Printed circuit board layout affects the performance of the

CLC016. The following are PCB layout rules for the CLC016:

Use a ground plane.

De-couple V

CC/VEE power pins with 0.01 µF ceramic ca-

pacitors placed

≤0.1” (3mm) from the power pins and

6.8 µF tantalum capacitors.

For long signal runs, match transmission lines to the de-

sired characteristic impedance for the input and output

lines.

Remove ground plane 0.025” (0.06mm) from all pads.

Remove ground plane from the area around the loop fil-

ter and frequency selection resistors.

Keep digital and analog lines sufficiently away from loop

filter or frequency selection resistors.

Avoid the use of sockets in production boards.

In proto-boards use a low-profile, low impedance, type

socket.

EVALUATION BOARD

An evaluation board layout and schematic are shown on the

following page. The art work shows the board solder masks,

trace layers, and ground plane.

To order an evaluation

board, contact your local sales representative or Na-

tional

support

center

and

request

part

number

CLC730057.

The evaluation board provides LEDs and switches to oper-

ate the PLL in various modes. The board allows the user to

select +5V or −5.2V power supplies, identified on the printed

board silk screen. Insert all tantalum capacitors as shown in

the schematic or silk screen. A complete bill of materials is

given in the following table. The components recommended

in the materials list are for SMPTE 259M standards.

DS100087-34

FIGURE 22. Jitter Measurement Setup

DS100087-35

FIGURE 23. Typical Jitter Histogram

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