TLF11752

September 1995

CGS74CT2524

1 to 4 Minimum Skew (300 ps) Clock Driver

General Description

These minimum skew clock drivers are designed for Clock

Generation and Support (CGS) applications operating at

high frequencies This device guarantees minimum output

skew across the outputs of a given device

Skew parameters are also provided as a means to measure

duty cycle requirements as those found in high speed clock-

ing systems The CGS74CT2524 is a minimum skew clock

driver with one input driving four outputs specifically de-

signed for signal generation and clock distribution applica-

tions

Features

Y

Y

Y

1 input to 4 outputs low skew clock distribution

Y

Y

Y

8-pin SOIC package

Y

Low dynamic power consumption above 20 MHz

Y

Guaranteed 2 kV ESD protection

Logic Symbol

TLF11752 – 1

The output pins act as a single entity and will follow the state of the CLK

when the clock distribution chip is selected

Pin Description

Pin Names

Descripton

CLK

Clock Input

Outputs

Truth Table

Inputs

Outputs

CLK

LL

HH

Connection Diagrams

Pin Assignment

SOIC (M)

TLF11752 – 2

TLF11752 – 3

C1995 National Semiconductor Corporation

RRD-B30M115Printed in U S A