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Data Sheet

AD9684

Rev. 0 | Page 63 of 64

APPLICATIONS INFORMATION

POWER SUPPLY RECOMMENDATIONS

The AD9684 must be powered by the following six supplies:

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD =

1.25 V, DRVDD = 1.25 V, and SPIVDD = 1.8 V. For applications

requiring an optimal high power efficiency and low noise

performance, it is recommended that the ADP2164 and ADP2370

switching regulators be used to convert the 3.3 V, 5.0 V, or 12 V

input rails to an intermediate rail (1.8 V and 3.8 V). These

intermediate rails are then postregulated by very low noise, low

dropout (LDO) regulators (ADP1741, ADP1740, and ADP125).

Figure 70 shows the recommended power supply scheme for

the AD9684.

ADP125

LDO

ADP2370

BUCK

REGULATOR

3.3V: AVDD3

ADP1741

LDO

1.25V: DVDD

ADP1740

LDO

1.25V: DRVDD

ADP1741

LDO

ADP2164

BUCK

REGULATOR

1.25V: AVDD1

ADP125

LDO

1.8V: SPIVDD

ADP1741

LDO

2.5V: AVDD2

3.3V

INPUT

5V/12V

INPUT

1.8V

3.8V

Figure 70. High Efficiency, Low Noise Power Solution for the AD9684

It is not necessary to split all of these power domains in all

cases. The recommended solution shown in Figure 70 provides

the lowest noise, highest efficiency power delivery system for

the AD9684. If only one 1.25 V supply is available, route to

AVDD1 first and then tap it off and isolate it with a ferrite bead

or a filter choke, preceded by decoupling capacitors for

SPIVDD, DVDD, and DRVDD, in that order. The user can

employ several different decoupling capacitors to cover both

high and low frequencies. These capacitors must be located

close to the point of entry at the PCB level and close to the

devices, with minimal trace lengths.

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