AD9613 datasheet(9/36 Pages) AD

tên linh kiện	AD9613

Giải thích chi tiết về linh kiện	12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

PDF	36 Pages

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nhà sản xuất	AD [Analog Devices]

Trang chủ	http://www.analog.com

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9 / 36 page

Data Sheet

AD9613

Rev. C | Page 9 of 36

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SYNC TIMING REQUIREMENTS

See Figure 3 for timing details

tSSYNC

SYNC to the rising edge of CLK setup time

0.3

tHSYNC

SYNC to the rising edge of CLK hold time

0.4

SPI TIMING REQUIREMENTS

See Figure 58 for SPI timing diagram

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tEN_SDIO

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge (not shown in Figure 58)

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge (not shown in Figure 58)

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