RT4723 datasheet(13/15 Pages) RICHTEK

13 / 15 page

RT4723

is a registered trademark of Richtek Technology Corporation.

DS4723-00

April

2016

www.richtek.com

The maximum power dissipation at TA = 25C can be

calculated by the following formula :

PD(MAX) = (125C  25C) / (49.8C/W) = 2W for

WL-CSP-15B 1.39x2.07 (BSC) package

The maximum power dissipation depends on the

operating ambient temperature for fixed TJ(MAX) and

thermal resistance,

JA. The derating curve in Figure 2

allows the designer to see the effect of rising ambient

temperature on the maximum power dissipation.

Figure 2. Derating Curve of Maximum Power

Dissipation

Layout Considerations

For the best performance of RT4723, the following

PCB layout guidelines should be strictly followed.



For good regulation, place the power components as

close to the IC as possible. The traces should be

wide and short especially for the high current output

loop.



The input and output bypass capacitor should be

placed as close to the IC as possible and connected

to the ground plane of the PCB.



The flying capacitor should be placed as close to the

C1P/C1N/C2P/C2N pin as possible to avoid noise

injection.



Minimize the size of the LXP node and keep the

traces wide and short. Care should be taken to avoid

running traces that carry any noise-sensitive signals

near LXP or high-current traces.



Separate power ground (PGND) and analog ground

(GND). Connect the GND and the PGND islands at

a single end. Make sure that there are no other

connections between these separate ground planes.

0.0

0.5

1.0

1.5

2.0

2.5

100

125

Ambient Temperature (°C)

Four-Layer PCB

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