LM98722CCMTSLASHNOPB datasheet(5/150 Pages) TI1

5 / 150 page

LM98722

www.ti.com

SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015

Pin Descriptions(1) (continued)

I/O

TYP

RES

DESCRIPTION

NO.

NAME

DOUT5/

Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS

Mode.

TXOUT2+

DOUT4/

Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode.

TXOUT2-

DOUT3/

Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS

Mode.

TXOUT1+

DOUT2/

Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.

TXOUT1-

DOUT1/

Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS

Mode.

TXOUT0+

DOUT0/

Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode.

TXOUT0-

DGND

Configurable sensor control output.

Power supply for the digital circuits. Bypass this supply pin with 0.1

μF capacitor. A

single 4.7

μF capacitor should be used between the supply and the VD, VR and VC

pins.

Power supply for the sensor control outputs. Bypass this supply pin with 0.1

μF

capacitor.

Output clock for registering output data when using CMOS outputs, or a configurable

CLKOUT/SH2

low speed sensor timing output.

SH3

Configurable low speed sensor timing output.

Configurable high speed sensor timing output.

PHIA1

Configurable high speed sensor timing output.

PHIA2

Configurable high speed sensor timing output.

DGND

Digital ground return.

Power supply for the sensor control outputs.

Bypass this supply pin with 0.1

μF capacitor.

PHIB1

Configurable high speed sensor timing output.

PHIB2

Configurable high speed sensor timing output.

SH4

Configurable low speed sensor timing output.

SH5

Configurable low speed sensor timing output.

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