EMC1186 datasheet(13/43 Pages) MICROCHIP

13 / 43 page

Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications

Datasheet

SMSC EMC1186

Revision 1.0 (07-11-13)

DATASHEET

Chapter 4 System Management Bus Interface Protocol

4.1

Communications Protocol

The EMC1186 communicates with a host controller, such as an SMSC SIO, through the SMBus. The

SMBus is a two-wire serial communication protocol between a computer host and its peripheral

devices. A detailed timing diagram is shown in Figure 4.1.

For the first 15ms after power-up the device may not respond to SMBus communications.

4.1.1

SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic

‘0’ state while the SMBus Clock line is in a logic ‘1’ state.

4.1.2

SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If

this RD / WR bit is a logic ‘0’, the SMBus Host is writing data to the client device. If this RD / WR bit

is a logic ‘1’, the SMBus Host is reading data from the client device.

The EMC1186-1 SMBus address is hard coded to 1001_100(r/w).

The EMC1186-2 SMBus address is hard coded to 1001_101(r/w).

4.1.3

SMBus Data Bytes

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

4.1.4

SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives. This is done by the client device

pulling the SMBus data line low after the 8th bit of each byte that is transmitted. This applies to the

Write Byte protocol.

Figure 4.1 SMBus Timing Diagram

SMDATA

SMCLK

BUF

S - Start Condition

P - Stop Condition

T HIGH

T LOW

HD:STA

SU:STO

HD:STA

HD:DAT

SU:DAT

SU:STA

FALL

RISE

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