IS67WVC4M16ALL datasheet(4/67 Pages) ISSI

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IS66WVC4M16ALL

IS67WVC4M16ALL

Rev. B | July 2012

www.issi.com – SRAM@issi.com

Signal Descriptions

All signals for the device are listed below in Table 1.

Symbol

Type

Description

VDD

Power Supply

Core Power supply (1.7V~1.95V)

VDDQ

Power Supply

I/O Power supply (1.7V~1.95V)

VSS

Power Supply

All VSS supply pins must be connected to Ground

VSSQ

Power Supply

All VSSQ supply pins must be connected to Ground

DQ0~DQ15

Input / Output

Data Inputs/Outputs (DQ0~DQ15)

A0~A21

Input

Address Input(A0~A21)

LB#

Input

Lower Byte select

UB#

Input

Upper Byte select

CE#

Input

Chip Enable/Select

OE#

Input

Output Enable

WE#

Input

Write Enable

CRE

Input

Control Register Enable: When CRE is HIGH, READ and WRITE operations

access registers.

ADV#

Input

Address Valid signal

Indicates that a valid address is present on the address inputs. Address

can be latched on the rising edge of ADV# during asynchronous Read and

Write operations. ADV# can be held LOW during asynchronous Read and

Write operations.

CLK

Input

Clock

Latches addresses and commands on the first rising CLK edge when

ADV# is active in synchronous mode. CLK must be kept static Low during

asynchronous Read/Write operations and Page Read access operations.

WAIT

Output

WAIT

Data valid signal during burst Read/Write operation. WAIT is used to

arbitrate collisions between refresh and Read/Write operation. WAIT is

also asserted at the end of a row unless wrapping within the burst length.

WAIT is asserted and should be ignored during asynchronous and page

mode operation. WAIT is gated by CE# and is high-Z when CE# is high.

Table 1. Signal Descriptions

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