ADC10664CIWM datasheet(8/14 Pages) NSC

8 / 14 page

Timing Diagrams

Functional Description

The ADC10662 and ADC10664 digitize an analog input sig-

nal to 10 bits accuracy by performing two lower-resolution

“flash” conversions. The first flash conversion provides the

six most significant bits (MSBs) of data, and the second flash

conversion provides the four least significant bits LSBs).

Figure 3 is a simplified block diagram of the converter. Near

the center of the diagram is a string of resistors. At the bot-

tom of the string of resistors are 16 resistors, each of which

has a value 1/1024 the resistance of the whole resistor

string. These lower 16 resistors (the LSB Ladder) therefore

have a voltage drop of 16/1024, or 1/64 of the total reference

voltage (V

REF+ −VREF−) across them. The remainder of the

resistor string is made up of eight groups of eight resistors

connected in series. These comprise the MSB Ladder. Each

section of the MSB Ladder has 1⁄8 of the total reference volt-

age across it, and each of the LSB resistors has 1/64 of the

total reference voltage across it. Tap points across these re-

sistors can be connected, in groups of sixteen, to the sixteen

comparators at the right of the diagram.

DS011192-7

FIGURE 1. Mode 1. The conversion time (t

CONV) is set by the internal timer.

DS011192-8

FIGURE 2. Mode 2 (RD Mode). The conversion time (t

CRD) includes the

sampling time and is determined by the internal timer.

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