ADC10158CIWM datasheet(7/23 Pages) NSC

7 / 23 page

Electrical Characteristics (Continued)

Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and

test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may de-

grade when the device is not operated under the listed test conditions.

Note 3: All voltages are measured with respect to GND, unless otherwise specified.

Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < V

− or V

IN > AV

+ or DV+), the current at that pin should be limited to 5 mA. The

20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.

Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum

allowable power dissipation at any temperature is PD = (TJmax −TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,

TJmax = 150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow: ADC10154 with BIN and CIN suffixes 65˚C/W, ADC10154 with BIJ,

CIJ and CMJ suffixes 49˚C/W, ADC10154 with BIWM and CIWM suffixes 72˚C/W, ADC10158 with BIN and CIN suffixes 59˚C/W, ADC10158 with BIJ, CIJ, and CMJ

suffixes 46˚C/W, ADC10158 with BIWM and CIWM suffixes 68˚C/W.

Note 6: Human body model, 100 pF capacitor discharged through a 1.5 k

Ω resistor.

Note 7: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post-1986 National Semi-

conductor Linear Data Book for other methods of soldering surface mount devices.

Note 8: Two on-chip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below V− supply or

one diode drop greater than V+ supply. Be careful during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause an input diode to conduct, es-

pecially at elevated temperatures, which will cause errors for analog inputs near full-scale. The specification allows 50 mV forward bias of either diode; this means

that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected chan-

nel will corrupt the reading of a selected channel. This means that if AV+ and DV+ are minimum (4.5 VDC) and V

− is a maximum (−4.5 V

DC) full scale must be ≤ ±4.55

VDC.

Note 9: A diode exists between AV+ and DV+ as shown below.

Note 10: Typicals are at TJ = TA = 25˚C and represent most likely parametric norm.

Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: One LSB is referenced to 10 bits of resolution.

Note 13: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.

Note 14: For DC Common Mode Error the only specification that is measured is offset error.

Note 15: Channel leakage current is measured after the channel selection.

Note 16: All the timing specifications are tested at the TTL logic levels, VIL = 0.8V for a falling edge and VIH = 2.0V for a rising.

DS011225-4

DS011225-5

To guarantee accuracy, it is required that the AV+ and DV+ be connected together to a power supply with separate bypass filter at each V+ pin.

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