TMS320C6743CPTP2 datasheet(7/151 Pages) TI1

7 / 151 page

TMS320C6743

www.ti.com

SPRS565D – APRIL 2009 – REVISED JUNE 2014

Device Overview

3.1

Device Characteristics

provides an overview of the C6743 Low power digital signal processor. The table shows significant

features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin

count.

Characteristics of the C6743 Processor

HARDWARE FEATURES

C6743

SDRAM only, 16-bit bus width, up to

EMIFB

128 MB (PTP)

128 MB (ZKB)

EMIFA

Asynchronous (8-bit bus width) RAM, Flash, NOR, NAND

Flash Card Interface

MMC and SD cards supported.

EDMA3

32 independent channels, 8 QDMA channels, 2 Transfer controllers

2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1

Timers

configurable as Watch Dog)

UART

2 (One with RTS and CTS flow control)

Peripherals

SPI

One with one hardware chip select

Not all peripherals pins

I2C

2 (both Master/Slave)

are available at the

same time (for more

Multichannel Audio Serial Port

2 (each with transmit/receive, FIFO buffer, 14/9 serializers)

detail, see the Device

[McASP]

Configurations section).

10/100 Ethernet MAC with

1 (RMII Interface)

Management Data I/O

eHRPWM

6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs

eCAP

3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs

eQEP

2 32-bit QEP channels with 4 inputs/channel

General-Purpose Input/Output

8 banks of 16-bit

Port

PRU Subsystem (PRUSS)

2 Programmable PRU Cores

Size (Bytes)

320KB RAM

DSP

32KB L1 Program (L1P)/Cache (up to 32KB)

On-Chip Memory

Organization

32KB L1 Data (L1D)/Cache (up to 32KB)

128KB Unified Mapped RAM/Cache (L2)

DSP Memories can be made accessible to EDMA3, and other peripherals.

C674x CPU ID + CPU

Control Status Register

0x1400

Rev ID

(CSR.[31:16])

C674x Megamodule

Revision ID Register

0x0000

Revision

(MM_REVID[15:0])

0x8B7DF02F (Silicon Revision 1.0)

JTAG BSDL_ID

DEVIDR0 register

0x8B7DF02F (Silicon Revision 1.1)

0x9B7DF02F (Silicon Revision 3.0, 2.1, and 2.0)

CPU Frequency

MHz

C674x DSP 375(/200) MHz

Core (V)

1.2 V

Voltage

I/O (V)

3.3 V

24 mm x 24 mm, 176-Pin, 0.5 mm

17 mm x 17 mm, 256-Ball 1 mm pitch,

Package

pitch, TQFP (PTP)

PBGA (ZKB)

Product Preview (PP),

Product Status(1)

Advance Information (AI),

or Production Data (PD)

(1)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Device Overview

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