M08045 datasheet(27/49 Pages) MA-COM

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Functional Description

M08035, M08045 Data Sheet V1

MACOM

™

080x5-DSH-001

On a Write cycle, any bits that follow the expected number of bits are ignored, and only the first 15 bits following SB

and OP are used. On a Read cycle, any extra clock cycles will result in the repeat of the data LSB. An invalid SB or

OP renders the operation undefined. The falling edge of xCS always resets the serial operation for a new Read or

Write cycle.

Detailed timing information is shown below.

Figure 4-7.

Four-Wire Sequential WRITE

Table 4-4.

Four-wire Interface Timing

Timing Symbol

Description

Min

Max

Unit

Tds

Data set-up time

—

Tdh

Data hold time

—

Tcs

xCS set-up time

—

Tch

xCS hold time

—

Tfreq, write

Four-wire interface write clock frequency

—

MHz

Tfreq, read

Four-wire interface clock read frequency,

DVDDIO=2.5 V or 3.3 V

—40

MHz

Four-wire interface read clock frequency, DVDDIO=1.8 V

—

MHz

Four-wire interface read clock frequency, DVDDIO=1.2 V

—

MHz

TDUTY

SCLK duty cycle

Tdd

Read data output delay

(measured with max 30 pF loading, DVDDIO=3.3 V)

SCLK

xCS

...

Address[7:0]

1st Data[7:0]

R/W

...

2nd Data[7:0]

3rd Data[7:0]

Tcs

Tdh

Tds

...

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