PI6LC4830 datasheet(2/11 Pages) PERICOM

2 / 11 page

PI6LC4830 Rev B

08/17/12

PI6LC4830

HiFlexTM Network Clock Generator

Pin Description

Pin Number Pin Name

Type

Description

20, 21, 23, 24,

26, 27

QA0+, QA0-, QA1+,

QA1-, QA2+, QA2-

Output (HCSL)

100MHz HCSL Outputs

9, 10

REF_Out+, REF_Out- Output (LVPECL)

25MHz LVPECL output from fundamental oscillator

core

Input

Crystal input pin

Output

Oscillator output pin

6, 7

IN+, IN-

Input (Differential)

HCSL/LVPECL/LVDS inputs

IN_SEL

Input (LVCMOS)

Low selects X1 and X2, High selects In+, In-. Internal

pull up is 100k Ohms

PLL_Byps

Input (LVCMOS)

If Low, output buffers are switched to the PLL. If High,

output buffers are switched to the input mux. Internal

100K-Ohm pulldown.

30, 3

QA_OE, QB_OE

Input (LVCMOS)

Low enables outputs, High selects high impedance

mode. Internal 100K-Ohm pulldown

VDD_OSC

Power

Power for xtal Osc core

VDD_PLL

Power

Power for digital portion of PLL circuitry

22, 29

VDD_Out

Power

Power for output buffers

VDDA_PLL

Power

Power for analog core of PLL

19, 25

GND

Power

Ground

QA_CMOS

Output (LVCMOS)

100MHz LVCMOS Output

QB_CMOS

Output (LVCMOS)

100/50MHz Selectable LVCMOS Output

VDD_OutA_SE

Power

Bank A LVCMOS Power

VDD_OutB_SE

Power

Bank B LVCMOS Power

QB_DIV2

Input (LVCMOS)

High selects 50MHz, Low selects 100MHz. Internal

100K-Ohm pull-up

IREF

Output

External resistor connection for internal current refer-

ence

VDD_REF_OUT

Power

Power for reference output

REF_OUT_OE

Input (LVCMOS)

Low enables outputs, High selects high impedance

mode. Internal 100K-Ohm pull-down.

VDD

Power

Power for Core

12-0238

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