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PI6LC48P0301

Rev. A

07/30/13

PI6LC48P0301

3-Output LVPECL Networking Clock Generator

AC Electrical Characteristics

LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND

Symbol

Parameter

Condition

Min.

Typ.

Max

Units

Output Frequency Range

Otuput Divider = ÷1

490

680

MHz

Otuput Divider = ÷2

245

340

MHz

Otuput Divider = ÷3

163.33

226.67

MHz

Otuput Divider = ÷4

122.5

170

MHz

Otuput Divider = ÷5

98

136

MHz

Otuput Divider = ÷8

61.25

85

MHz

25

ps

Output @ Same Frequencies

70

ps

Output @ Different Frequencies

200

ps

RMS Phase Jitter,

625MHz,

(1.875MHz - 20MHz)

0.14

ps

625MHz,

(12kHz - 20MHz)

0.32

ps

312.5MHz,

(1.875MHz - 20MHz)

0.15

ps

312.5MHz,

(12kHz - 20MHz)

0.32

ps

156.25MHz,

(1.875MHz - 20MHz)

0.16

ps

156.25MHz,

(12kHz - 20MHz)

0.32

ps

125MHz,

(1.875MHz - 20MHz)

0.17

ps

125MHz,

(12kHz - 20MHz)

0.32

ps

Output Rise/Fall Time

20% to 80%

400

ps

o

DC

Output Duty Cycle

Measured at the dif-

ferential cross point

Otuput Divider

= ÷1

47

53

%

Other divider

values

47

53

%

Note:

1. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.

2. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.

3. Please refer to the Phase Noise Plots.

4. This parameter is defined in accordance with JEDEC Standard 65.

13-0116