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PI6LC48P02

Rev. C

08/13/15

PI6LC48P02

2-Output LVPECL Fibre Channel (FC) and Ethernet Clock Generator

Phase Noise Plots

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LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND

Symbol

Parameter

Condition

Min.

Typ.

Max

Units

Output Rise/Fall Time

20% to 80%

400

ps

o

DC

Output Duty Cycle

48

52

%

Note:

1. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.

2. Please refer to the Phase Noise Plots.

3. This parameter is defined in accordance with JEDEC Standard 65.

15-0102