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PI6LC48L0201

Rev. A

07/23/2013

PI6LC48L0201

2-Output LVDS Networking Clock Generator

Symbol Parameter

Condition

Min

Typ

Max

Units

Differential Output Voltage

V

247

454

mV

V

247

454

V

50

mV

V

50

Output Offset Voltage

V

1.125

1.375

V

V

1.125

1.375

V

50

mV

V

50

Symbol Parameter

Condition

Min.

Typ.

Max

Units

Output Frequency

N_SEL[1:0] = 00

140

170

MHz

N_SEL[1:0] = 01

112

136

MHz

N_SEL[1:0] = 10

56

68

MHz

Outputs @ same loading

50

ps

RMS Phase Jitter,

156.25MHz,

(1.875MHz - 20MHz)

0.2

ps

156.25MHz,

(12kHz - 20MHz)

0.32

ps

125MHz,

(1.875MHz - 20MHz)

0.2

ps

125MHz,

(12kHz - 20MHz)

0.31

ps

62.5MHz,

(1.875MHz - 20MHz)

0.4

ps

62.5MHz,

(12kHz - 20MHz)

0.5

ps

Output Rise/Fall Time

20% to 80%

400

ps

odc

Output Duty Cycle

48

52

%

Note:

1. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.

2. Please refer to the Phase Noise Plots.

3. This parameter is defined in accordance with JEDEC Standard 65.

13-0115