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PI6LC48H02 bảng dữ liệu(PDF) 7 Page - Pericom Semiconductor Corporation |
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PI6LC48H02 bảng dữ liệu(HTML) 7 Page - Pericom Semiconductor Corporation |
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7 / 9 page ![]() 7 www.pericom.com PI6LC48H02 Rev.C 04/07/2014 All trademarks are property of their respective owners. PI6LC48H02 PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs HCSL Output AC Characteristics (VDD = 3.3V ±10%, TA = -40°C to +85°C) Symbol Parameter Conditions Min. Typ. Max. Unit FIN Input Frequency 25 MHz FOUT Output Frequency 25 200 MHz VOH Output High Voltage (1,2) 100 MHz HCSL output @ VDD = 3.3V 660 800 900 mV VOL Output Low Voltage(1,2) -150 0 mV VCPA Crossing Point Voltage(1,2) Absolute 250 350 550 mV VCN Crossing Point Voltage(1,2,4) Variation over all edges 140 mV JCC Jitter, Cycle-to-Cycle(1,3) 35 60 ps JPhase RMS Phase Jitter, (Random) 100MHz 25MHz Xtal input, 12kHz - 20MHz 0.32 0.5 ps 125MHz 25MHz Xtal input, 12kHz - 20MHz 0.3 0.5 ps JRMS2.0 PCIe 2.0 RMS Jitter PCIe 2.0 Test Method @ 100MHz Output 3.1 ps JRMS3.0 PCIe 3.0 RMS Jitter PLL L-BW @ 2M & 5M 1st H3 1.42 3 ps PLL L-BW @ 2M & 4M 1st H3 2.05 3 ps PLL H-BW @ 2M & 5M 1st H3 0.45 1 ps PLL H-BW @ 2M & 4M 1st H3 0.45 1 ps tOR Rise Time(1,2) From 0.175V to 0.525V 175 700 ps tOF Fall Time(1,2) From 0.525V to 0.175V 175 700 ps TSKEW Skew between outputs At Crossing Point Voltage 50 ps TDUTY-CYCLE Duty Cycle(1,3) 45 55 % TOE Output Enable Time(5) All outputs 10 μs TOT Output Disable Time(5) All outputs 10 μs tSTABLE Stabilization Time From Power-up VDD=3.3V 3.0 ms Notes: 1. RL = 50-Ohm with CL = 2 pF 2. Single-ended waveform 3. Differential waveform 4. Measured at the crossing point 5. CLK pins are tri-stated when OE is LOW 14-0044 |
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