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9

Truth Table

TTL/CMOS Control Voltages

Worst Case Step Error

Between Successive Attenuation States

HMC467LP3

v00.0403

2 dB LSB GaAs MMIC 2-BIT DIGITAL

POSITIVE CONTROL ATTENUATOR, DC - 6.0 GHz

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

2 dB

4 dB

6 dB

FREQUENCY (GHz)

State

Bias Condition

Low

0 to 0.8 Vdc @ -5 uA Typ.

High

+2.0 to +5.0 Vdc @ 40 uA Typ.

Control Voltage Input

Attenuation Setting

RF1 - RF2

V1

4 dB

V2

2 dB

High

High

Reference I.L.

High

Low

2 dB

Low

High

4 dB

Low

Low

6 dB

Max. Atten.

Any combination of the above states will provide an attenuation

approximately equal to the sum of the bits selected.

Bias Voltage & Current

Vdd Range= +5.0 Vdc ± 10%

Vdd

(Vdc)

Idd (Typ.)

(mA)

Idd (Max.)

(mA)

+5.0

0.7

1.2