PI6CFGL402B datasheet(5/8 Pages) PERICOM

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PI6CFGL402B

Low Power PCIe 3.0 Clock Generator with 4 HCSL Outputs

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03/03/15

Symbol

Parameters

Condition

Min.

Type Max. Units

TSTAB

Clk Stabilization1,2

From VDD Power-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

0.6

fMODIN

Input SS Modulation

Frequency1

Allowable Frequency

(Triangular Modulation)

31.500 33

kHz

tOE

Output Enable Time1

All outputs

μs

tOT

Output Disable Time1 All outputs

μs

tSTABLE

From power-up to

VDD = 3.3V1

From Power-up VDD = 3.3V

3.0

tSPREAD

Setting period after

spread change1

Setting period after spread change

3.0

Note:

1.Guaranteedbydesignandcharacterization,not100%testedinproduction.

2.Controlinputmustbemonotonicfrom20%to80%ofinputswing.InputFrequencyCapacitance

3.Timefromdeassertionuntiloutputsare>200mV

4.DIF_INinput

Electrical Characteristics–CLK 0.7V Low Power HCSL Outputs (TA = -40~85oC; Supply Voltage VDD

= 3.3V +/-10%; VDDO = 1.8V +/-10%; 100MHz output frequency, See Test Loads for Loading Conditions)

Symbol

Parameters

Condition

Min.

Type Max.

Units

Trf

Slew rate1,2,3

1.1

4.5

V/ns

VHIGH

Voltage High1

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope aver-

aging on)

660

900

VLOW

Voltage Low1

-150

150

Vmax

Max Voltage1

Measurement on single ended signal using

absolute value. (Scope averaging off)

1150

Vmin

Min Voltage1

-300

Vswing

Vswing1,2

Scope averaging off

300

Vcross_abs

Crossing Voltage (abs)1,5

Scope averaging off

250

550

Δ-Vcross

Crossing Voltage (var)1,6

Scope averaging off

140

tDC

Duty Cycle1

Measured differentially, PLL Mode

tskew

Skew, Output to Output1 VT = 50%

tjcyc-cyc

Jitter, Cycle to cycle1,2

PLL mode

Note:

1.Guaranteedbydesignandcharacterization,not100%testedinproduction.

2.Measuredfromdifferentialwaveform

3.SlewrateismeasuredthroughtheVswingvoltagerangecenteredarounddifferential0V.Thisresultsina+/-150mVwindowarounddifferential0V.

4.MatchingappliestorisingedgerateforClockandfallingedgerateforClock#.Itismeasuredusinga+/-75mVwindowcenteredontheaveragecrosspoint

whereClockrisingmeetsClock#falling.Themediancrosspointisusedtocalculatethevoltagethresholdstheoscilloscopeistousefortheedgeratecalcula-

tions.

5.VcrossisdefinedasvoltagewhereClock=Clock#measuredonacomponenttestboardandonlyappliestothedifferentialrisingedge(i.e.Clockrisingand

Clock#falling).

6.ThetotalvariationofallVcrossmeasurementsinanyparticularsystem.NotethatthisisasubsetofVcross_min/max(Vcrossabsolute)allowed.Theintentis

tolimitVcrossinducedmodulationbysettingΔ-VcrosstobesmallerthanVcrossabsolute.

15-0032

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