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PI6CDBL401B

Rev.C

03/23/16

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PI6CDBL401B

4-Output Low Power PCIE GEN1-2-3 Buffer

SMBus Address Selection Table

SADR

Address

+ Read / Write bit

State of SADR on first application of CKPWRGD_PD#

0

1101011

1/0

M

1101100

1/0

1

1101101

1/0

Power Management Table

CKPWRGD_PD#

CLK_IN

SMBus OEx bit

OEx# Pin

CLKx

PLL

True O/P

Comp. O/P

0

x

x

x

Low

Low

Off

1

Running

0

x

Low

Low

1

Running

1

0

Running

Running

1

Running

x

1

Low

Low

1. If bypass mode is selected, the PLL will be off, and outputs will be running

Power Connections

Pin Number

Description

VDD

GND

4

7

Input receiver analog

9

8

Digital Power

16, 25

15, 26, 30

DIF outputs

21

20

PLL Analog

PLL Operating Mode

HiBW_BypM_LoBW# MODE

Byte1 [7:6]

Readback

Byte1 [4:3]

Control

0

PLL Lo BW 00, 10

00, 10

M

Bypass

01

01

1

PLL Hi BW 11

11

Pin Configuration

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

OE2#

CLK2#

CLK2

VDDA3.3

GNDA

CLK1#

CLK1

OE1#

HIBW_BYPM_LOBW#

FB_DNC

FB_DNC#

VDDR3.3

CLK_IN

CLK_IN#

GNDR

GNDDIG

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

PI6CDBL401B

16-0064