PI6C49019 datasheet(2/16 Pages) PERICOM

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PI6C49019

Rev. B

06/25/13

PI6C49019

Low Power Networking Clock Generator

Pin Description

Pin#

Pin Name

Pin Type

Pin Description

VDD

Power

3.3V Supply Pin

Cdd

Input

Input pin for off chip bypass capacitor. Connect to 0.01

μF capacitor

PCIE2N

Output

Differential 100 MHz HCSL PCI Express Clock output

PCIE2

Output

Differential 100 MHz HCSL PCI Express Clock output

VDD

Power

3.3V Supply Pin

GND

Power

Ground

VDD

Power

3.3V Supply Pin

PCIE3N

Output

Differential 100 MHz HCSL PCI Express Clock output

PCIE3

Output

Differential 100 MHz HCSL PCI Express Clock output

GND

Power

Ground

VDD

Power

3.3V Supply Pin

SCLK

Input

SMBus clock input

SDATA

I/O

SMBus data input

GND

Power

Ground

33M/67M

Output

33.33 MHz or 67.33 MHz LVCMOS output. Tri-stated

with a weak pull-down when disabled.

Pin List

VDD

Cdd

PCIE0N

PCIE0

GND

VDD

SCLK

SDATA

GND

VDD

33M/67M

GND

PD_RESET

25M

125M/REF

PCIE1N

PCIE2

PCIE2N

VDD

PCIE3N

PCIE3

GND

VDDO2

VDD

PCIE1

GND

VDD

GND

VDD

48M

VDD

GND

VDD

19M

VDD

13-0103

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