PI6C49018 datasheet(3/13 Pages) PERICOM

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PI6C49018

Rev. A

12/10/2014

PI6C49018

Low Power Networking Clock Generator

Pin Description

Pin#

Pin Name

Pin Type

Pin Description

PD_RESET

Input

Global reset input powers down PLLs plus tri-states

outputs and sets the I2C tables to their default state

when pulled low. Controlled by external POR

Crystal input. Connect to 25 MHz fundamental mode

crystal or clock

Crystal output. Connect to 25 MHz fundamental mode

crystal. Float for clock input

VDDX

Power

3.3V Supply Pin for oscillator

VDDO

Power

125 MHz output supply voltage. Connect to +2.5 V

125M

Output

125 MHz, +2.5 V LVCMOS output. Tri-stated with a

weak pull-down when disabled

GND

Power

Ground

VDD

Power

3.3V Supply Pin

66.66M

Output

66.66 MHz LVCMOS output. Tri-stated with a weak

pull-down when disabled

GND

Power

Ground

VDD

Power

3.3V Supply Pin

GND

Power

Ground

60M

Output

60 MHz LVCMOS output. Tri-state with weak pull-

down when disabled

VDD

Power

3.3V Supply Pin

GND

Power

Ground

VDD

Power

3.3V Supply Pin

PCIE0N

Output

Differential 100 MHz PCI Express Clock output

PCIE0

Output

Differential 100 MHz PCI Express Clock output

PCIE1

Output

Differential 100 MHz PCI Express Clock output

PCIE1N

Output

Differential 100 MHz PCI Express Clock output

VDD

Power

3.3V Supply Pin

GND

Power

Ground

VDD

Power

3.3V Supply Pin

Cdd

Input

Input pin for off chip bypass capacitor. Connect to 0.01

μF capacitor

PCIE2N

Output

Differential 100 MHz PCI Express Clock output

PCIE2

Output

Differential 100 MHz PCI Express Clock output

14-0209

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