NJW4841

- 4 -

Ver.2015-02-27

 TIMING CHART

10%

IN

OUT

90%

tr

90%

10%

tf

90%

10%

 TYPICALAPPLICATION

NJW4841

GND

VDD

IN

FET

VDD

GND

OUT

IN

10

F

0.1

F

NJW4841

GND

VDD

IN

IGBT

VDD

GND

OUT

IN

10

F

0.1

F

 APPLICATION TIPS

In the application that does a high-speed switching of NJW4841, because the current flow corresponds to the input

frequency, the substrate (PCB) layout becomes an important.

NJW4841 is driving the High-side/Low-side SW gate with high speed to reduce switching losses. The transient voltage

is generated by parasitic inductance and a high-speed current change of high side and low side SW.

You should attempt the transient voltage decrease by making a current loop area minimize as much as possible.

Therefore, you should make a current flowing line thick and short as much as possible.

You should insert a bypass capacitor between the VDD pin and the GND pin to prevent malfunction by transient

voltage and/or exceed maximum input voltage rating. The recommended bypass capacitor is low ESR and fine high

frequency characteristic (NJRC recommends 0.1

smoothing capacitor (NJRC recommends 10

F or more). However, you should use large capacitor by sufficient

evaluation (assessment) due to load condition and/or application use environment. (There is a possibility that the supply

voltage rises by inductive kickback when the supply current of the inductive load is large.) The bypass capacitors should

be connected as near as possible to the VDD pin.