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XC9141 bảng dữ liệu(PDF) 13 Page - Torex Semiconductor |
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XC9141 bảng dữ liệu(HTML) 13 Page - Torex Semiconductor |
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13 / 30 page ![]() 13/30 XC9141/XC9142 Series ■ NOTE ON USE (Continued) 16) Instructions for pattern layouts 1. In order to stabilize VBAT voltage level, we recommend that a by-pass capacitor CIN is connected as close as possible to the BAT and GND pins. 2. Please mount each external component as close to the IC as possible. 3. Place external components as close to the IC as possible and use thick and short traces to reduce the circuit impedance. 4. Make sure that the PCB GND traces are thick and wide as possible. GND voltage level fluctuation created by high ground current at the time of switching may cause instability of the IC. 5. The internal driver transistors bring on heat because of the IIN current and ON resistance of the driver transistors. < Example of pattern layout> SOT-25 PCB mounted 1st layer 2nd layer USP-6C PCB mounted 1st layer 2nd layer WLP-6-01 PCB mounted 1st layer 2nd layer 6. Note on mounting (WLP-6-01) 6-1. Mount pad design should be optimized for user's conditions. 6-2. Sn-AG-Cu is used for the package terminals. If eutectic solder is used, mounting reliability is decreased. Please do not use eutectic solder paste. 6-3. When underfill agent is used to increase interfacial bonding strength, please take enough evaluation for selection. Some underfill materials and applied conditions may decrease bonding reliability. 6-4. The IC has exposed surface of silicon material in the top marking face and sides so that it is weak against mechanical damages. Please take care of handling to avoid cracks and breaks. 6-5. The IC has exposed surface of silicon material in the top marking face and sides. Please use the IC with keeping the circuit open (avoiding short-circuit from the out). 6-6. Semi-transparent resin is coated on the circuit face of the package. Please be noted that the usage under strong lights may affects device performance. |
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