Functional Descriptions

31544-DSH-001-B

Mindspeed Technologies

®

21

Mindspeed Proprietary and Confidential

4.5

Digital Interface

The 4-wire serial interface is selected with pin.MODE_SEL =H. The M31544/64 serial interface supports daisy

chain mode in order to control several devices.

4.5.1

4-Wire Serial Write

Figure 4-4 Illustrates the Serial Write Mode. To initiate the 16-bit long write sequence, xCS is driven low before the

rising edge of SCLK. On each rising edge of the clock, the 16 bits consisting of R/xW = 0 for write, ADDR (7-bit)

and DATA (8-bit), are latched into the input shift register through SI. After the last data bit is sent, xCS must be

driven high to complete the write operation.

4.5.2

4-Wire Serial Read

Figure 4-5 Illustrates the Serial Read Mode. To initiate the 32-bit long read sequence, xCS is driven low before the

rising edge of SCLK. On each rising edge of the clock, the first16 bits consisting of R/xW = 1 for read, ADDR (7-bit)

and dummy DATA (8 x “1” bits), are latched into the input shift register through SI. After the 16th bit is sent, xCS

must be toggled to start the second part of the operation. The second set of 16 x “1” bits are latched into the input

shift register through SI while the register address and data requested in the first part of the read transaction are

shifted out on SO on the failing edge of the clock. Finally, xCS must be driven high to complete the read operation.

Figure 4-4.

4-wire Serial WRITE Timing Diagram

Figure 4-5.

4-wire Serial READ Timing Diagram

DON’T CARE

SCLK

xCS

Tcs

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

0

SI

SO

Tch

Tcot

Tds

Tdh

Tzdd

Tddz

DON’T CARE

SCLK

xCS

Tcs

12

34

5678

9

15 16

A6

A5

A4

A3

A2

A1

A0

1

SI

SO

Tch

Tcot

Tds

Tdh

Tzdd

Tddz

Tcs

1

2

8

9

10

11

12

13

14

15 16

Tch

Tcot

Tzdd

Tddz

A6

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

1

1

Tdd

8 bits

16 bits

...

...