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SP78LC00 bảng dữ liệu(PDF) 3 Page - Sipex Corporation |
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SP78LC00 bảng dữ liệu(HTML) 3 Page - Sipex Corporation |
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3 / 10 page ![]() 3 Rev. 5/19/03 SP78LC00 100mA CMOS LDO Regulator © Copyright 2003 Sipex Corporation Note 1. Exceeding the absolute maximum rating may damage the device. Note 2. The device is not guaranteed to function outside its operating rating. Note 3. The maximum allowable power dissipation at any T A (ambient temperature) is PD (MAX) = (TJ (MAX) – TA) / q JA. Exceeding the maximum allowable power dissipation will result in excessive die temperature, and the regulator will go into thermal shutdown. The q JA of the SP78LC00 (all versions) is 220°C/W mounted on a PC board with minimum copper area (see “Thermal Considerations” section for further details). Note 4. Output voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range. Note 5. Load Regulation is measured at constant junction temperature using low duty cycle pulse testing. Parts are tested for load regulation in the load range; from 0.1mA to 100mA. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Note 6. Dropout Voltage is defined as the input to output differential at which the output voltage drops 2% below its nominal value measured at 1V differential. Note 7. Ground pin current is the regulator quiescent current. The total current drawn from the supply is the sum of the load current plus the ground pin current. Note 8. Thermal regulation is defined as the change in output voltage at a time ”t” after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a 100mA load pulse at V IN = 6V for t = 10ms. ELECTRICAL SPECIFICATIONS: Continued VIN = VOUT +1V, IL = 100µA, CIN = 1.0µF, COUT = 1.0µF, TJ = 25°C , bold values indicate -40°C ≤ TJ ≤ 125°C unless otherwise noted. PIN NUMBER NAME FUNCTION 1 GND Ground 2INSupply Input Voltage 3OUT Regulator Output Voltage 4,5 NC No Connection PIN ASSIGNMENTS FUNCTIONAL DIAGRAM V IN Current Limit + - VREF 1.25V 1.20V Bandgap REF and Thermal Shutdown GND R1 OUT IN R2 C OUT VOUT C IN |
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