LP3910 datasheet(8/72 Pages) TI1

8 / 72 page

LP3910

SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015

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7.5 Electrical Characteristics

Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, and limits apply for TJ = 25°C.

(1) (2) (3) (4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

All circuits off except for POR and battery

Battery standby supply

IQ_BATT

monitor. No adapter or USB power

µA

current

connected.

All circuits off except for POR and battery

Battery standby supply

monitor. No adapter or USB power

IQ_BATT

µA

current

connected.

TJ = 0°C to 125°C

VPOR

Power-on reset threshold

VDD falling edge

1.9

Thermal shutdown

TSD

160

°C

threshold

Thermal shutdown

TSDH

°C

hysteresis

TTH-ALERT

Thermal interrupt threshold

115

°C

VDDIO

IO supply

2.5

VDD

Internal system clock

FCLK

MHz

frequency

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the

most likely norm.

(3)

Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.

(4)

This specification is ensured by design. Not tested during production.

7.6 Electrical Characteristics: I

2C Interface

Unless otherwise noted, VDDIO = 3.6 V, and minimum and maximum limits apply for TJ = 0°C to 125°C.

(1) (2) (3) (4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIL

Low level input voltage

I2C_SDA & I2C_SCL

0.3 × VDDIO

VIH

High level input voltage

I2C_SDA & I2C_SCL

0.7 × VDDIO

VOL

Low level output voltage

I2C_SDA & I2C_SCL

0.2 × VDDIO

VHYS

Schmitt trigger input hysterisis

I2C_SDA & I2C_SCL

0.1 × VDDIO

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Minimum and maximum limits are specified by design, test, or statistical analysis.

(3)

Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.

(4)

This specification is ensured by design.

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