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CY7C1386S bảng dữ liệu(PDF) 21 Page - Cypress Semiconductor

tên linh kiện CY7C1386S
Giải thích chi tiết về linh kiện  18-Mbit (512 K 횞 36) Pipelined DCD Sync SRAM
PDF  22 Pages
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nhà sản xuất  CYPRESS [Cypress Semiconductor]
Trang chủ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1386S bảng dữ liệu(HTML) 21 Page - Cypress Semiconductor

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CY7C1386S
Document Number: 001-43823 Rev. *E
Page 21 of 22
*D
3571224
04/03/2012
PRIT
Updated Features (Removed 250 MHz, 200 MHz frequencies related
information, removed 119-ball BGA package and 165-ball FBGA package
related information).
Updated Functional Description (Removed the Note “For best practices or
recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines on www.cypress.com.” and its reference,
removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA
packages only. 119-ball BGA is offered only in 1 chip enable.” and its
reference).
Updated Selection Guide (Removed 250 MHz, 200 MHz frequencies related
information).
Removed Logic Block Diagram – CY7C1387S.
Updated Pin Configurations (Removed CY7C1387S related information,
removed 119-ball BGA package and 165-ball FBGA package related
information).
Updated Pin Definitions (Removed the Note “CE3, CE2 are for 100-pin TQFP
and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip
enable.” and its reference, removed JTAG related information).
Updated Functional Overview (Removed the Note “CE3, CE2 are for 100-pin
TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip
enable.” and its reference).
Updated Truth Table (Removed CY7C1387S related information).
Removed Truth Table for Read/Write (Corresponding to CY7C1387S).
Removed IEEE 1149.1 Serial Boundary Scan (JTAG).
Removed TAP Controller State Diagram.
Removed TAP Controller Block Diagram.
Removed TAP Timing.
Removed TAP AC Switching Characteristics.
Removed 3.3 V TAP AC Test Conditions.
Removed 3.3 V TAP AC Output Load Equivalent.
Removed 2.5 V TAP AC Test Conditions.
Removed 2.5 V TAP AC Output Load Equivalent.
Removed TAP DC Electrical Characteristics and Operating Conditions.
Removed Identification Register Definitions.
Removed Scan Register Sizes.
Removed Identification Codes.
Removed Boundary Scan Order.
Updated Operating Range (Removed Industrial Temperature range).
Updated Electrical Characteristics (Removed 250 MHz, 200 MHz frequencies
related information).
Updated Capacitance (Removed 119-ball BGA package and 165-ball FBGA
package related information).
Updated Thermal Resistance (Removed 119-ball BGA package and 165-ball
FBGA package related information).
Updated Switching Characteristics (Removed 250 MHz, 200 MHz frequencies
related information).
Updated Package Diagrams (Removed 119-ball BGA package and 165-ball
FBGA package related information).
Replaced all instances of IO with I/O across the document.
*E
3978170
04/22/2013
PRIT
No technical updates. Completing Sunset Review.
Document History Page (continued)
Document Title: CY7C1386S, 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM
Document Number: 001-43823
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change



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