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SP3232 bảng dữ liệu(PDF) 10 Page - Sipex Corporation

tên linh kiện SP3232
Giải thích chi tiết về linh kiện  3.3V, 1000 Kbps RS-232 Transceivers
PDF  20 Pages
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nhà sản xuất  SIPEX [Sipex Corporation]
Trang chủ  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP3232 bảng dữ liệu(HTML) 10 Page - Sipex Corporation

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Rev. A Date:12/11/03
SP3222EU/3232EU 3.3V, 1000kbps RS-232 Transceivers
© Copyright 2003 Sipex Corporation
10
Since receiver input is usually from a trans-
mission line where long cable lengths and
system interference can degrade the signal and
inject noise, the inputs have a typical hyster-
esis margin of 300mV. Should an input be left
unconnected, a 5k
Ω pulldown resistor to
ground will commit the output of the receiver
to a HIGH state.
Charge Pump
The charge pump is a Sipex–patented design
(5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply
consists of a regulated dual charge pump that
provides output voltages 5.5V regardless of
the input voltage (V
CC) over the +3.0V to
+5.5V range.
In most circumstances, decoupling the power
supply can be achieved adequately using a
0.1
µF bypass capacitor at C5 (refer to Figures
9 and 10). In applications that are sensitive to
power-supply noise, decouple V
CC to ground
with a capacitor of the same value as charge-
pump capacitor C1. Physically connect
bypass capacitors as close to the IC as
possible.
The charge pumps operate in a discontinuous
mode using an internal oscillator. If the
output voltages are less than a magnitude of
5.5V, the charge pumps are enabled. If the
output voltage exceed a magnitude of 5.5V,
the charge pumps are disabled. This oscillator
controls the four phases of the voltage
shifting. A description of each phase follows.
Phase 1
— V
SS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C
1 and C2 are initially charged to VCC. Cl
+ is
then switched to GND and the charge in C
1
– is
transferred to C
2
–. Since C
2
+ is connected to
V
CC, the voltage potential across capacitor C2
is now 2 times V
CC.
Phase 2
— V
SS transfer — Phase two of the clock
connects the negative terminal of C
2 to the VSS
storage capacitor and the positive terminal of
C
2 to GND. This transfers a negative gener-
ated voltage to C
3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage
to C
3, the positive side of capacitor C1 is
switched to V
CC and the negative side is
connected to GND.
Phase 3
— V
DD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C
1 produces –VCC in the
negative terminal of C
1, which is applied to
the negative side of capacitor C
2. Since C2
+ is
at V
CC, the voltage potential across C2 is 2
times V
CC.
Phase 4
— V
DD transfer — The fourth phase of the
clock connects the negative terminal of C
2 to
GND, and transfers this positive generated
voltage across C
2 to C4, the VDD storage
capacitor. This voltage is regulated to +5.5V.
At this voltage, the internal oscillator is
disabled. Simultaneous with the transfer of
the voltage to C
4, the positive side of capaci-
tor C
1 is switched to VCC and the negative side
Table 2. SP3222EU Truth Table Logic for Shutdown
and Enable Control
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