SP3203ECY datasheet(10/16 Pages) SIPEX

10 / 16 page

Rev.

2/7/01

SP3203E

duces –V

CC in the negative terminal of C1, which

is applied to the negative side of capacitor C

Since C

+ is at V

CC, the voltage potential across

2 is 2 times VCC.

DD Transfer-Phase 4 (Figure 16)

The fourth phase of the clock connects the nega-

tive terminal of C

2 to GND, and transfers this

positive generated voltage across C

2 to C4, the

DD storage capacitor. This voltage is regulated

to +5.5V. At this voltage, the internal oscillator

is disabled. Simultaneous with the transfer of the

voltage to C

4, positive side of capacitor C1 is

switched to V

CC and the negative side is con-

nected to GND, allowing the charge pump cycle

to begin again. The charge pump cycle will

continue as long as the operational conditions for

the internal oscillator are present.

Since both V+ and V– are separately generated

from V

CC, in a no–load condition, V

+ and V– will

be symmetrical. Older charge pump approaches

that generate V– from V+ will show a decrease in

the magnitude of V– compared to V+ due to the

inherent ineffiencies in the design.

The clock rate for the charge pump is typically

operates at 250kHz. The external capacitors are

usually 0.1

µF with a 16V breakdown voltage

rating.

L Supply Level

Current RS-232 serial tranceivers are designed

with fixed 5V or 3.3V TTL input/output voltages

levels. The VL function in the SP3203E allows

the end user to set the TTL input/output voltage

levels independent of V

CC. By connecting VL to

the main logic bus of system, the TTL input/

output limits and threshold are reset to interface

with the on board low voltage logic circuity.

)

((

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