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UCC28704 bảng dữ liệu(PDF) 13 Page - Texas Instruments

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tên linh kiện UCC28704
Giải thích chi tiết về linh kiện  High-Efficiency Off-Line CV
PDF  44 Pages
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UCC28704 bảng dữ liệu(HTML) 13 Page - Texas Instruments

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0 V
VS ring p-p
(scaled)
tDM_BLANK
tLK_RESET
tDMAG
tSW
Entering Wait State
IPP < IPP(max)
RS2/(RS1+RS2)
13
UCC28704
www.ti.com
SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016
Product Folder Links: UCC28704
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Feature Description (continued)
The UCC28704 VS signal sampler includes signal discrimination methods to ensure an accurate sample of the
output voltage from the auxiliary winding. There are however critical details of the auxiliary winding signal to
ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any
subsequent leakage inductance ring. Refer to Figure 14 for a detailed illustration of waveform criteria to ensure a
reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset
pedestal, TLK_RESET in Figure 14. Since this can mimic the waveform of the secondary current decay, followed by
a sharp downslope, it is important to keep the leakage reset time less than 750 ns for IPRI minimum, and less
than 3.0 µs for IPRI maximum. The second detail is the amplitude of ringing on the VAUX waveform following
tLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately 250 mVp-p at least 250 ns
before the end of the demagnetization time, tDMAG. If there is a concern with excessive ringing, it usually occurs
during light or no load conditions, when tDMAG is at the minimum, tDMAG(min). The tolerable ripple on VS is scaled
up to the auxiliary winding voltage by RS1 and RS2, and is equal to 250 mV × (RS1+RS2) / RS2. The snubber
designs can be designed to allow the ripple voltage to meeting these requirements.
As mentioned in Device Functional Modes, when IPP < IPP(max), the device operation enters a “Wait” state during
each switching cycle of its non-switching portion as shown in Figure 14. In the Wait state, the device bias current
changes to IWAIT (typical 70 µA) from IRUN (typical 2.3 mA), reducing its bias power to help boost efficiency at light
load and to reduce standby load power.
Figure 14. Auxiliary Waveform Details



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