AD6676EBZ datasheet(50/90 Pages) AD

50 / 90 page

AD6676

Data Sheet

Rev. A | Page 50 of 90

Preemphasis

Preemphasis enables the receiver eye diagram mask to be met in

conditions where the interconnect insertion loss does not meet

the JESD204B specification. The preemphasis feature is controlled

via Register 0x1EF and must be used only when the receiver

cannot recover the clock due to excessive insertion loss. Under

normal conditions, it is disabled to conserve power. Additionally,

enabling and setting too high a deemphasis value on a short link

may cause the receiver eye diagram to fail or lead to potential

EMI issues. For these reasons, consider the use of preemphasis

only in instances where meeting the receiver eye diagram mask

is a challenge. See the Register Memory Map section for details.

Serializer PLL

This PLL generates the serializer clock that is equal to the

JESD204B lane rate. The on-chip controller automatically

configures the PLL parameters based on the user specified IQ

data rate (FADC/M) and number of lanes. The status of the PLL

lock can be checked via the PLL_LCK status bit in Register 0x2DC.

This read only bit lets the user know if the PLL has achieved a

lock for the specific setup.

CONFIGURING THE JESD204B LINK

The AD6676 has one JESD204B link. The serial outputs

(SERDOUT0± and SERDOUT1±) are part of one JESD204B

link. The basic parameters that determine the link setup are:



L is the number of lanes per link



M is the number of converters per link



F is the number of octets per frame

The maximum and minimum specified lane rates for the

AD6676 are 5.333 Gbps and 3.072 Gbps, respectively. For this

reason, the AD6676 supports a single lane interface for IQ data

rates (fDATA_IQ) from 76.8 MSPS to 133.3 MSPS and a two lane

interface from 153.6 MSPS to 266.7 MSPS.

The lane line rate is related to the JESD204B parameters using

the following equation:





Rate

Line

Lane

DATA_IQ



 40

(14)

where:

DEC

ADC

DATA_IQ



The decimation ratio (DEC) is the parameter programmed into

Table 19 shows the JESD204B output configurations supported

based on fDATA_IQ.

Table 19. JESD204B Output Configurations

No. Virtual Converters

Supported (same as M)

fDATA_IQ (MSPS)

JESD Serial Line Rate

76.8 to 133.3

40 × fDATA_IQ

For F = 4, K ≥ 5

153.6 to 266.7

20 × fDATA_IQ

For F = 2, K ≥ 9

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