TMDS181I datasheet(13/58 Pages) TI1

13 / 58 page

TMDS181, TMDS181I

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SLASE75A – AUGUST 2015 – REVISED OCTOBER 2015

TMDS Switching Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX(2)

UNIT

tJITC1(2.0)

DR = 6 Gbps: CLK = 150 MHz

0.3

Tbit

3.4 Gbps < Rbit ≤ 3.712 Gps

TX_TERM_CTL = NC; PRE_SEL = NC;

0.4

OE = H

3.712 Gbps < Rbit < 5.94 Gbps

–0.0332Rbit

2 +

Total output data jitter

tJITD2

TX_TERM_CTL = NC; PRE_SEL = NC;

0.2312Rbit +

Tbit

See Figure 14

OE = H

0.1998

5.94 Gbps

≤ Rbit ≤ 6.0 Gbps

TX_TERM_CTL = NC; PRE_SEL = NC;

0.6

OE = H

6.11 HPD Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX(2)

UNIT

tPD(HPD)

Propagation delay from HPD_SNK to

See Figure 16; not valid during

120

HPD_SRC; rising edge and falling edge(2)

switching time

tT(HPD)

HPD logical disconnected timeout

See Figure 17

(1)

The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted

(2)

The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted

6.12 DDC and I

2C Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Rise time of both SDA and SCL signals

VCC = 3.3 V

300

Fall time of both SDA and SCL signals

300

tHIGH

Pulse duration, SCL high

0.6

μs

tLOW

Pulse duration, SCL low

1.3

μs

tSU1

Setup time, SDA to SCL

100

tST, STA

Setup time, SCL to start condition

0.6

μs

tHD,STA

Hold time, start condition to SCL

0.6

μs

tST,STO

Setup time, SCL to stop condition

0.6

μs

t(BUF)

Bus free time between stop and start condition

1.3

μs

Source to sink: 100kbps pattern;

tPLH1

Propagation delay time, low-to-high-level output

360

Cb(Sink) = 400 pF(1); see Figure 20

tPHL1

Propagation delay time, high-to-low-level output

230

Sink to source: 100kbps pattern;

tPLH2

Propagation delay time, low-to-high-level output

250

Cb(Source) = 100 pF(1); see Figure 21

tPHL2

Propagation delay time, high-to-low-level output

200

(1)

Cb = total capacitance of one bus line in pF.

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